Tae-Hwan Kim

Professor, School of Electronics and Information Engineering, Korea Aerospace University

Room #214, Electronics Building, Korea Aerospace University, 76 Hanggongdaehak-ro, Deogyang-gu, Goyang-si, Gyeonggi-do, Republic of Korea (10540)

📞+82-10-9953☎️7098

taehwan.kim 💌 kau.kr

🔗https://cas.kau.ac.kr

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🏢 Employment

• Tenured Full Professor, Associate Professor, Assistant Professor
  • School of Electronics and Info. Engineering, Korea Aerospace University, Goyang, Korea
  • Sept. 1, 2011 - Present
• Visiting Professor
  • Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
  • Sept. 2025 – Aug. 2026
• Senior Engineer
  • DMC R\&D Center, Samsung Electronics Co. Ltd., Suwon, Korea
  • Aug. 1, 2010 - Aug. 30, 2011
  • Role: Research and Development of Baseband IC for WLAN

🎓 Education

• Ph.D. Electrical Engineering,
  • KAIST, Daejeon, Korea (Feb. 23, 2007 ~ Aug. 20, 2010)
  • Best Paper Award for Ph.D. Dissertation
• M.S. Electrical Engineering,
  • KAIST, Daejeon, Korea (Mar.1, 2005 ~ Feb. 2, 2007)
• B.S. Electrical Engineering,
  • YONSEI University, Seoul, Korea, (Mar. 2, 1998 ~ Feb. 28, 2005)
  • Graduation with High Honors

🏆 Awards & Honors

• Silver Prize, ASP-DAC University LSI Design Contest (Supervising)
  • Jan. 24, 2024
• Best Student Paper Award, IEIE Summer Conference (Supervising)
  • July 1, 2022
• Yearly Best Paper Award, IEIE Semiconductor Society
  • Dec. 16, 2019
• Yearly Best Paper Award (Signal Processing), IEIE
  • Nov. 22, 2019
• Best Design Award, IDEC SoC Congress Chip Design Contest (Supervising)
  • July 4, 2019
• Best Poster Award, ISOCC Chip Design Contest (Supervising)
  • Nov. 13, 2018
• Best Instructor Award, Intel (Altera) FPGA Design Contest
  • Dec. 1, 2018
• Best Oral Paper Award, SoC Conference (Supervising)
  • May 11, 2018
• Best Poster Award, ISOCC Chip Design Contest (Supervising)
  • Nov. 6, 2017
• Best Demo Award, IDEC SoC Congress Chip Design Contest (Supervising)
  • June 29, 2017
• Best Student Paper Award, IEIE Summer Conference (Supervising)
  • July 1, 2017
• Best Demo Award, IDEC SoC Congress - Chip Design Contest (Supervising)
  • June 29, 2017
• Best Instructor Award, Intel (Altera) FPGA Design Contest
  • Dec. 22, 2016
• Distinguished Paper Award, IEIE SoC Conference
  • Gwang-Ho Lee and Tae-Hwan Kim
  • May 16, 2015
• Meritorious Engineering Award, Gyeonggi-do
  • Oct. 30, 2013
• Best Paper Award for Ph. D. Dissertation, KAIST
  • Feb. 11, 2011
• Awards for Excellence in Research (3-times), Dept. Electrical Engineering, KAIST
  • April 3, 2008
  • April 6, 2009
  • April 8, 2010
• IP Design Contest - Bronze Medal (3rd place), Korea Intellectual Property Office
  • Tae-Hwan Kim and Young-Joo Lee
  • Dec. 8, 2008
• IP Design Contest - Best Design Award (1st place), Dongbu Hitek
  • Ji-Hoon Kim, Tae-Hwan Kim, and Hae-Soo Jeon
  • July 23, 2007
• Graduation with High Honors, YONSEI University
  • Feb. 28, 2005

🔬 Current Research Interests

• VLSI Architectures for Artificial Intelligence
  • On-Device Inference and Train: CNN/RNN/Transformer Variants
  • Binary Neural Networks
• VLSI Architectures for Communication Signal Processing Systems
  • Channel Decoder Architectures: Polar Decoders.
  • MIMO-OFDM Receivers: Detection & Synchronization
• VLSI Architectures for Multimedia Signal Processing Systems
  • SLAM: Large-Scale Non-Linear Optimization at Edge
  • Deweathering Systems: Digital Correction of Optical Distortion, Dehazing
  • Sound Synthesis Systems
• General-purpose Microprocessor Architectures
  • Multiprocessor Architectures for Embedded Applications
  • Memory System Architectures

🧑🏻‍🏫 Relevant Coursework

• Digital Logic Design, Computer Arithmetic, SoC Architecture, VLSI, Digital Integrated Circuits, Computer System & Microprocessor Architecture, Digital Signal Processing, Wireless Communication Systems, etc.

📜 Publications

International Journals

1. Jun-Hyung Lee and Tae-Hwan Kim, “A Low-Complexity Programmable Normalization Processor for Transformer Inference,” IEEE Embedded Systems Letters, Under Review.
2. Myoung-Hoon Shim, Sae-Byeok Jeong, Si-Kyu Nam, and Tae-Hwan Kim, “US-BIP: A Unified and Saturation-Aware Processor for Efficient Binary Neural Network Inference,” IEEE Embedded Systems Letters, To be published.
3. Tae-Hwan Kim, Jeongwon Ha, Wonwoo Lee, and Taehun Ko, “Softmex: Lightweight Softmax Compute Engines Based on Exponentiation Units,” IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, To be published.
4. Jun-Hyung Lee, Seon-Hee Oh, and Tae-Hwan Kim, “MiniBRNN: A Low-Resource Inference Processor for Binary-Weight Recurrent Neural Networks Based on Speculative Operation Pruning and Interleaved Thread Scheduling,” IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, To be published.
5. Gil-Ho Kwak, Jaeho Kim, and Tae-Hwan Kim, “SR-BIP: A Soft Error-Resilient Binary Neural Network Inference Processor,” IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 4, no. 7, pp. 2822-2826, July 2025.
6. Gil-Ho Kwak and Tae-Hwan Kim, “BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy with 1.9 Mbit On-Chip Parameters in a 28 nm FPGA,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 71, no. 11, pp. 4673-4677, Nov. 2024.
7. Su-Jung Lee and Tae-Hwan Kim, “Latency and Accuracy Optimization for Binary Neural Network Inference with Locality-Aware Operation Skipping,” IET Electronics Letters, vol. 60, no. 2, pp. 1-4, Feb. 2024.
8. Jinsung Yoon, Neungyun Kim, Donghyun Lee, Su-Jung Lee, Gil-Ho Kwak, and Tae-Hwan Kim, “A Resource-Efficient Keyword Spotting System Based on a One-Dimensional Binary Convolutional Neural Network,” MDPI Electronics, vol. 12, no. 8: 3964, Sept. 2023.
9. Jiho Kim and Tae-Hwan Kim, “ROSETTA: A Resource and Energy-Efficient Inference Processor for Recurrent Neural Networks Based on Programmable Data Formats and Dynamic Activation Pruning,” IEEE Trans. Emerging Topics in Computing, vol. 11, no. 3, 650-663, Sept. 2023.
10. Su-Jung Lee, Gil-Ho Kwak, and Tae-Hwan Kim, “TORRES: A Resource-Efficient Inference Processor for Binary Convolutional Neural Networks Based on Locality-Aware Operation Skipping,” MDPI Electronics, vol. 11, no. 21: 3534, Oct. 2022.
11. Jinwon Kim, Jiho Kim, and Tae-Hwan Kim, “AERO: A 1.28 MOP/s/LUT Reconfigurable Inference Processor for Recurrent Neural Networks in a Resource-Limited FPGA,” MDPI Electronics, vol. 10, no. 11: 1249, May 2021.
12. Changho Ryu and Tae-Hwan Kim, “Low-Complexity Training for Binary Convolutional Neural Networks Based on Clipping-Aware Weight Update,” IEICE Trans. Information & Systems, vol. e104-d, no. 6, June 2021.
13. Tae-Hwan Kim and Jihoon Shin, “A Resource-Efficient Inference Accelerator for Binary Convolutional Neural Networks in a Low-Cost FPGA,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 68, no. 1, pp. 451-455, Jan. 2021.
14. Tae-Hwan Kim, Jihoon Shin, and Kyungchan Choi, “IOTA: A 1.7-TOP/J Inference Processor for Binary Convolutional Neural Networks with 4.7K LUTs in a Tiny FPGA,” IET Electronics Letters, vol. 56, no. 20, pp. 1041-1044, Sept. 2020.
15. Jihoon Shin and Tae-Hwan Kim, “Fast Inference of Binarized Convolutional Neural Networks Exploiting Max Pooling with Modified Block Structure,” IEICE Trans. Information & Systems, vol. e103-d, no. 3, pp. 706-710, Mar 2019.
16. Hye-Yeon Yoon and Tae-Hwan Kim, “Efficient Successive-Cancellation Polar Decoder Based on Redundant LLR Representation,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 65, no. 12, pp. 1944-1948, Mar. 2018.
17. Tae-Hwan Kim, “An Efficient Barrel Distortion Correction Processor for Bayer-Pattern Images,” IEEE Access, vol. 6, pp. 28239-28248, May 2018.
18. Yongmin Park, Minsang Kim, and Tae-Hwan Kim, “Fast Execution Schemes for Dark-Channel-Prior-Based Outdoor Video Dehazing,” IEEE Access, vol. 6, pp. 10003-10014, Feb. 2018.
19. Hye-Yeon Yun, Gwang-Ho Lee, and Tae-Hwan Kim, “Efficient Sphere Decoding Based on Regular Detection Tree for Generalized Spatial Modulation MIMO Systems,” IEICE Trans. Communications, vol. e101-b, no. 1, pp. 223-231, Jan. 2018.
20. Gwang-Ho Lee and Tae-Hwan Kim, “Implementation of a Near-Optimal Detector for Spatial Modulation MIMO Systems,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 63, no. 10, pp. 954-958, Feb. 2016.
21. Tae-Hwan Kim and Jin-Whee Kim, “Partitioned Scheduling for Sphere Decoding with Runtime Constraints for Practical MIMO Communication Systems,” International Journal of Communications Systems, vol. 29, no. 9, pp. 1474-1481, May 2016.
22. Tae-Hwan Kim and Kwang-Ho Yi, “Low-complexity symbol detection based on modified beam search for spatial modulation MIMO systems,” Electronics Letters, vol. 51, no. 19, pp. 1546-1548, Sept. 2015.
23. Tae-Hwan Kim, “Low-Complexity Constant Multiplication for Layer Processing in MIMO Symbol Detection,” Electronics Letters, vol. 51, no. 13, pp. 989-991, June 2015.
24. Tae-Hwan Kim, “Fast Barrel Distortion Correction for Wide-angle Cameras,” IEICE Trans. Information & Systems, vol. e98-d, no. 7, pp. 1413-1416, July 2015.
25. Tae-Hwan Kim, “Low-complexity Sorted QR Decomposition for MIMO Systems,” IEEE Trans. Wireless Communications, vol. 13, no. 3, pp. 1388-1396, Mar. 2014.
26. Tae-Hwan Kim, “Early Eviction Technique for Low-complexity MIMO Symbol Detection Based on Dijkstra’s Algorithm,” IEICE Trans. Fundamentals, vol. e96-a, no. 11, pp. 2302-2305, Mar. 2014.
27. Tae-Hwan Kim and In-Cheol Park, “Efficient Pruning for Infinity-norm Sphere Decoding,” IEICE Trans. Communications, vol. e94-d, no. 11, pp. 2979-2988, Nov. 2010.
28. In-Cheol Park and Tae-Hwan Kim, “Multiplier-less and Table-less Linear Approximation for Square-related Functions,” IEICE Trans. Information & Systems, vol. e93-d, no. 11, pp. 2979-2988, Nov. 2010.
29. Tae-Hwan Kim and In-Cheol Park, “Small-Area and Low-Energy K-Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2753-2761, Oct. 2010.
30. Tae-Hwan Kim and In-Cheol Park, “High-throughput and Area-efficient MIMO Symbol Detection Based on Modified Dijkstra’s Search,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 7, pp. 1756-1766, July 2010.
31. Tae-Hwan Kim, Young-Joo Lee, and In-Cheol Park, “Design of a Scalable and Programmable Sound Synthesizer,” IEEE Tran. Very Large Scale Integration Systems, vol. 18, no. 6, pp. 875-886, June 2010.
32. Tae-Hwan Kim and In-Cheol Park, “Low-power and High-accurate Synchronization for IEEE 802.16d Systems,” IEEE Trans. Very Large Scale Integration Systems, vol. 16, no. 12, pp. 1620-1630, Dec. 2008.

International Conferences

1. Sae-Byeok Jeong and Tae-Hwan Kim, “Δ²-PSUM: A Low-Latency Soft-Error-Resilient Binary Neural Network Inference Processor,” in Proc. the 34th IEEE Int’l Symp. Field-Programmable Custom Computing Machines (FCCM), pp. 1-4, May. 2026.
2. Jisu Kim and Tae-Hwan Kim, “StabiFreeze: Early Stopping for Training Binary Neural Networks via Internal Dynamics Stabilization,” in Proc. 31st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-7, Jan. 2026.
3. Jun-Hyeong Lee and Tae-Hwan Kim, “A Low-Complexity Processor Supporting Layer and RMS Normalization,” in Proc. IBM IEEE CAS/EDS – AI Compute Symposium, pp. 1-2, Nov. 2025.
4. Jaeho Kim, Saebyuk Jeong, and Tae-Hwan Kim, “Error-Resilient Binary Neural Network Inference Based on Gradient-Based Selective Recompute,” in Proc. IEEE Int’l Symp. System-On-Chip Conference (ISOCC), pp. 1-4, Oct. 2025.
5. Tae-Hwan Kim, Su-Jung Lee, Sohye Lee, and Jiyoung Lee, “Locality-Aware Adaptive Threshold Scaling for Efficient Binary Neural Networks Inference,” in Proc. The 7th IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 1-4, Apr. 2025.
6. Gil-Ho Kwak and Tae-Hwan Kim, “BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy with 1.9 Mbit On-Chip Parameters in a 28 nm FPGA,” IEEE International Symp. Integrated Circuits & Systems (ISICAS), pp. 1-5, Oct. 2024.
7. Gil-Ho Kwak and Tae-Hwan Kim, “Error-Resilient Binary Neural Network Inference with Selective Recompute-Based Error Correction,” in Proc. IEEE Int’l Symp. System-On-Chip Conference (ISOCC), pp. 1-2, Aug. 2024.
8. Gil-Ho Kwak and Tae-Hwan Kim, “A 17.01 MOP/s/LUT binary neural network inference processor showing 87.81% CIFAR10 accuracy with 2.6M-bit on-chip parameters in a 28nm FPGA,” in Proc. 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-2, Feb. 2024.
9. Jinsung Yoon, Donghyun Lee, Neungyun Kim, Su-Jung Lee, Gil-Ho Kwak, and Tae-Hwan Kim, “A Real-Time Keyword Spotting System Based on an End-To-End Binary Convolutional Neural Network in FPGA,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOLChips 26), pp. 1-3, Apr. 2023.
10. Jiho Kim, Kwoanyoung Park, and Tae-Hwan Kim, “A Reconfigurable Inference Processor for Recurrent Neural Networks Based on Programmable Data Format in a Resource-Limited FPGA,” in Proc. 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-2, Jan. 2022.
11. Hye-Yeon Yoon, Seung-Jun Hwang, and Tae-Hwan Kim, “A 655Mbps Successive-Cancellation Decoder for a 1024-Bit Polar Code in 180nm CMOS,” in Proc. Asian Solid-State Circuit Conf. (ASSCC), pp. 1-4, Nov. 2018.
12. Hye-Yeon Yoon and Tae-Hwan Kim, “Generalized Tree Architecture for Efficient Successive-Cancellation Polar Decoding,” in Proc. IEEE Int’l Conf. Computer Design (ICCD), pp. 1-8, Oct. 2018.
13. Tae-Hwan Kim and Yongmin Park, “High-Quality and Fast Dehazing Method Based on Modified Median Dark Channel,” in Proc. IEEE Region-10 Conf. (TENCON), pp. 1-3, Oct. 2018.
14. Yongmin Park, Seongchan Kim, and Tae-Hwan Kim, “SIMD Implementation of Binarized Convolutional Neural Network,” in Proc. IEEE Int’l Conf. Consumer Electronics (ICCE), pp. 1-2, Jan. 2018.
15. Yongmin Park and Tae-Hwan Kim, “A Video Dehazing System Based on Fast Airlight Estimation,” in Proc. IEEE Global Conf. Signal and Information Processing (GLOBALSIP), pp. 1-4, Nov. 2017.
16. Hye-Yeon Yun and Tae-Hwan Kim, “Low-Complexity Symbol Detection for Generalized Spatial Modulation MIMO Systems,” in Proc. IEEE Vehicular Technology Conf. (VTC) 2017-Fall.
17. Hye-Yeon Yun, Gwang-Ho Lee, and Tae-Hwan Kim, “A 686Mbps 1.85mm2 Near-Optimal Symbol Detector for Spatial Modulation MIMO Systems in 0.18μm CMOS,” in Proc. 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-2, Jan. 2017.
18. Gwang-Ho Lee, Hye-Yeon Yun, and Tae-Hwan Kim, “A Near-Optimal Detector for Spatial Modulation MIMO Systems,” in Proc. IEEE Int’l Symp. Circuits and Systems (ISCAS), pp. 1-4, May 2016.
19. Tae-Hwan Kim and Jin-Hwee Kim, “Partitioned scheduling for sphere decoding with runtime constraints for practical MIMO communication systems,” in Proc. Int’l Symp. Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 721-725, Aug. 2015.
20. Hui-Sung Jung and Tae-Hwan Kim, “An Efficient Processor for Joint Barrel Distortion Correction and Color Demosaicking,” in Proc. IEEE Int’l Symp. Circuits and Systems (ISCAS), pp. 1782-1785, May 2015.
21. Won-Tae Kim, Hyun-Woo Bae, and Tae-Hwan Kim, “Fast and Efficient Haze Removal Using Dark Channel Prior,” in Proc. IEEE Int’l Conf. Consumer Electronics (ICCE), pp. 360-361, Jan. 2015.
22. Tae-Hwan Kim, “Low-complexity Sorted QR Decomposition for MIMO Systems Based on Pairwise Column Symmetrization,” in Proc. IEEE Wireless Communications and Networking Conference (WCNC), pp. 1281-1286, Sept. 2014.
23. Won-Tae Kim, Hui-Sung Jung, Gwang-Ho Lee, and Tae-Hwan Kim, “A High-Speed and Low-Complexity Lens Distortion Correction Processor for Wide-Angle Cameras,” in Proc. 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 39-40, Jan. 2014.
24. Tae-Hwan Kim and In-Cheol Park, “A 2.6Gb/s 1.56mm2 Near-Optimal MIMO Detector in 0.18μm CMOS,” in Proc. Custom Integrated Circuits Conf. (CICC), pp. 1-4, Sept. 2010.
25. Tae-Hwan Kim and In-Cheol Park, “Small-Area and Low-Energy K-Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding,” in Proc. Int’l Symp. Low Power Electronics and Design (ISLPED), pp. 231-236, Aug. 2010.
26. In-Cheol Park and Tae-Hwan Kim, “Multiplier-less and Table-less Linear Approximation for Square and Square-root,” in Proc. IEEE Int’l Conf. Computer Design (ICCD), pp. 378-383, Oct. 2009.
27. Tae-Hwan Kim and In-Cheol Park, “Implementation of a High-throughput and Area-efficient MIMO Detector Based on Modified Dijkstra’s Search,” in Proc. IEEE Global Communication Conference (GLOBECOM), pp. 1-6, Nov. 2009.
28. Tae-Hwan Kim, Young-Joo Lee, and In-Cheol Park, “A Scalable and Programmable Sound Synthesizer,” in Proc. IEEE Int’l Symp. Circuits and Systems (ISCAS), pp. 1855-1858, May 2009.
29. Tae-Hwan Kim, Young-Joo Lee and In-Cheol Park, “Design of a Scalable Sound Synthesizer,” in Proc. IEEE Int’l SoC Design Conference (ISOCC), vol. 03, pp. 56-57, Nov. 2008.
30. Tae-Hwan Kim and In-Cheol Park, “Time-domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset,” in Proc. IEEE Vehicular Technology Conf. (VTC), pp. 1186-1190, May 2008.
31. Tae-Hwan Kim and In-Cheol Park, “Area and Power Efficient Design of Coarse Time Synchronizer and Frequency Offset Estimator for Fixed WiMAX Systems,” in Proc. 13th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 111-112, Mar. 2008.
32. Tae-Hwan Kim and In-Cheol Park, “Two-step Approach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS), pp. 193-198, Oct. 2007.

Domestic (Korean) Journals & Conferences

1. 정새벽, 조용기, 김태환, “신경망의 비트 폭에 따른 내성 분석 및 고찰,” 항공우주시스템공학회 춘계학술대회 논문집, 2026년 5월.
2. 이준형, 김태환, “FPGA 기반 온-보드 LLM 추론 시스템 설계와 구현,” 항공우주시스템공학회 춘계학술대회 논문집, 2025년 4월.
3. 이준형, 김태환, “경량 회귀 신경망 추론 시스템을 이용한 레이더 이미지 분류 구현,” 한국반도체학술대회 논문집, 2025년 1월.
4. 김재호, 김태환, “CW레이더와 이진 신경망을 기반으로 하는 드론 분류 및 거리 추정 시스템,” 반도체공학회 동계종합학술대회 논문집, 2025년 1월.
5. 김재호, 윤진성, 곽길호, 이수정, 김태환, “이진 신경망 추론 엔진 기반 경량 레이더 이미지 분류 시스템,” 한국전자파학회 하계 학술대회 논문집, 2024년 7월.
6. 이준형, 오선희, 김태환, “이진 가중치 회귀 신경망의 추론을 위한 저 복잡도 프로세서의 설계 및 구현,” 반도체공학회 하계 학술대회 논문집, 2024년 7월.
7. 이지영, 이소혜, 오선희, 김태환, “트랜스포머 추론 가속을 위한 하드웨어-소프트웨어 통합 시스템,” 대한전자공학회 논문지, vol. 61, no. 7, pp. 663-671, 2024년 7월.
8. 오선희, 이준형, 김태환, “효율적인 장단기 메모리의 추론 과정 처리를 위한 Speculative Activation Pruning 기법,” 대한전자공학회 논문지, vol. 61, no. 3, pp. 60-67, 2024년 3월.
9. 곽길호, 김태환, “이진화된 스트라이드 컨벌루션 신경망 기반의 저 복잡도 저 지연 추론 가속기,” 대한전자공학회 하계학술대회 논문집, pp. 408-411, 2023년 6월.
10. 오선희, 이준형, 김태환, “장단기 메모리의 고속 추론을 위한 순차적인 레인 처리 방법,” 대한전자공학회 하계학술대회 논문집, pp. 2149-2151, 2023년 6월.
11. 김능윤, 오선희, 김태환, “적은 파라미터의 경량 이진 신경망 모델,” 대한전자공학회 논문지, vol. 59, no. 12, pp. 65-72, 2022년 12월.
12. 이수정, 곽길호, 김태환, “End-to-End 신경망 기반 Keyword Spotting 시스템의 효율적인 구현,” 대한전자공학회 추계학술대회 논문집, pp. 135-137, 2022년 11월.
13. 오선희, 김능윤, 김태환, “이진화된 신경망의 파라미터 감소를 위한 효과적인 기법,” 대한전자공학회 하계학술대회 논문집, pp. 938-941, 2022년 6월.
14. 홍성재, 김지호, 김태환, “RNN 추론 프로세서를 위한 통합 검증 시스템,” 대한전자공학회 하계학술대회 논문집, pp. 1918-1921, 2022년 6월.
15. 류창호, 이형석, 김태환, “이진화된 신경망을 위한 효율적인 학습 가속 시스템,” 대한전자공학회 논문지, vol. 59, no. 1, pp. 3-9, 2022년 1월.
16. 김지호, 신지훈, 김태환, “Convolutional LSTM 모델 기반의 짧은 지연 시간을 갖는베어링 결함 진단,” 대한전자공학회 논문지, vol. 59, no. 1, pp. 124-130, 2022년 1월.
17. 이채은, 이수정, 김태환, “효율적인 Processing-In-Memory 구현을 위해 Truncation 현상을 고려한 이진화된 신경망,” 대한전자공학회 논문지, vol. 58, no. 12, pp. 27-32, 2021년 12월.
18. 양해찬, 박상준, 박관영, 사재현, 김태환, “효율적인 Capsule Network 추론 시스템의 설계 및 FPGA 구현,” 대한전자공학회 논문지, vol. 58, no. 11, pp. 39-47, 2021년 11월.
19. 김영재, 문지훈, 곽길호, 김태환, “합성곱 신경망의 병렬 학습 시스템 구현,” 대한전자공학회 추계학술대회, pp. 706-708, 2021년 11월.
20. 류창호, 이형석, 김태환, “클리핑 효과를 고려한 고속의 이진화된 신경망 학습​,” 한국반도체학술대회 논문집, 2021년 1월.
21. 박윤성, 류창호, 김태환, “임베디드 딥 러닝 시스템을 위한 On-Device 학습 최적화,” 대한전자공학회 하계학술대회 논문집, pp. 2236-2238, 2020년 8월.
22. 김진원, 김태환, “Simplified Successive Cancellation 알고리즘을 위한 효율적인 Polar 디코더의 설계 및 구현,” 대한전자공학회 논문지, vol. 57, no. 7, pp. 15-21, 2020년 7월.
23. 최경찬, 김태환, “이진화된 컨벌루션 신경망 기반의 추론을 위한 효율적인 워크로드 분할,” 대한전자공학회 논문지, vol. 57, no. 6, pp. 19-27, 2020년 6월.
24. 최경찬, 박윤성, 김태환, “강화학습을 위한 이진화된 컨벌루션 신경망 가속 프로세서,” 한국반도체학술대회 논문집, 2020년 2월.
25. 최경찬, 신지훈, 김태환, “이진화된 컨벌루션 신경망을 위한 낮은 복잡도의 추론 가속 프로세서,” 대한전자공학회 논문지, vol. 57, no. 11, pp. 53-69, 2020년 1월.
26. 황승준, 박현진, 김태환, “이중 비트 복호 및 중첩된 스케쥴링 기법에 기반한 고성능 준 병렬 극 복호기,” 대한전자공학회 논문지, vol. 55, no. 11, pp. 25-31, 2018년 11월.
27. 신지훈, 김철기, 김태환, “사운드 이벤트 감지를 통한 기계 상태 모니터링,” 대한전자공학회 논문지, vol. 55, no. 11, pp. 84-90, 2018년 11월.
28. 김성찬, 신지훈, 박용민, 김태환, “이진화된 컨벌류션 신경망의 효율적인 SIMD 구현,” 대한전자공학회 논문지, vol. 55, no. 1, pp. 49-56, 2018년 1월.
29. 박용민, 김태환, “OpenCL 기반의 상위 레벨 합성 기술을 이용한 고성능 안개 제거 시스템의 소프트웨어-하드웨어 복합설계,” 대한전자공학회 논문지, vol. 54, no. 8, pp. 1165-1172, 2017년 8월.
30. 윤혜연, 김태환, “제한된 연산량을 갖는 Dijkstra 탐색 기반의 스피어 디코딩,” 대한전자공학회 논문지, vol. 54, no. 7, pp. 1000-1006, 2017년 7월.
31. 김민상, 김병오, 박용민, 김태환, “효율적인 구현을 위한 안개제거 방법의 최적화,” 대한전자공학회 논문지, vol. 53, no. 10, pp. 1504-1511, 2016년 10월.
32. 박용민, 김병오, 김민상, 김태환, “효율적인 동영상 안개 제거를 위한 안개제거 알고리즘의 최적화,” 대한전자공학회 하계학술대회 논문집, pp. 727-720, 2016년 6월.
33. 문선아, 홍진우, 김원태, 김태환, “광각 카메라를 위한 저복잡도 비네팅 및 베럴 왜곡 보정 프로세서,” 대한전자공학회 논문지, vol. 52, no. 9, pp. 36-44, 2015년 9월.
34. 문선아, 김원태, 김태환, “이중 다크 채널에 기반한 고속 고품질의 안개 제거 방법,” 한국방송공학회 논문지, vol. 20, no. 5, pp. 697-705, 2015년 9월.
35. 박민우, 이상우, 김태환, “다중 입력 다중 출력 통신 시스템을 위한 저 복잡도의 joint QR decomposition-lattice reduction 프로세서,” 대한전자공학회 논문지, vol. 52, no. 8, pp. 40-48, 2015년 8월.
36. 김원태, 김태환, “이중 다크 채널 연산을 적용한 고속 고품질의 안개 제거 방법,” 대한전자공학회 하계 학술대회 논문집, 2015년 6월.
37. 김원태, 정희성, 김태환, “FPGA implementation of a barrel and vignetting distortion correction processor for wide-angle cameras,” 한국반도체학술대회 논문집, 2015년 1월.
38. 김원태, 배현우, 김태환, “전달량 보정에 기반한 고속, 고품질의 안개 제거 방법,” 대한전자공학회논문지, vol. 51, no. 11, pp. 2563-2571, 2014년 11월.
39. 이광호, 김태환, “MML 알고리즘 기반의 저 복잡도 고 성능의 MIMO 심볼 검파기의 구현,” 대한전자공학회 하계학술대회 논문집, 2014년 6월.
40. 배현우, 김태환, “전달량 보정에 기반한 고품질 안개 제거 알고리즘,” 대한전자공학회 하계학술대회 논문집, 2014년 6월.
41. 이광호, 김태환, “256 QAM까지 지원 가능한 저 복잡도 고 성능의 MIMO 심볼 검파기,” 대한전자공학회논문지, vol. 51, no. 6, pp. 1162-1170, 2014년 6월.
42. 정희성, 박윤주, 김태환, “컬러 디모자이킹이 결합된 저 복잡도의 실시간 배럴 왜곡 보정 프로세서,” 대한전자공학회논문지, vol. 51, no. 9, pp. 1943-1962, 2014년 9월.
43. 이길범, 정상진, 김태환, 이명진, “멀티코어 프로세서 기반의 영상 감시 시스템을 위한 침입탐지 가속화,” 대한전자공학회논문지, vol. 50, no. 12, pp. 3079-3087, 2013년 12월.
44. 정희성, 김원태, 이광호, 김태환, “광각카메라를 위한 저복잡도 실시간 베럴 왜곡 보정 프로세서의 설계 및 구현,” 대한전자공학회논문지, vol. 50, no. 6, pp. 1447-1453, 2013년 6월.
45. 김은찬, 김봉진, 김태환, 박인철, “Coherence Management Unit Saving Modified Lines Internally for Multicore Systems,” 대한전자공학회 하계학술대회 논문집, vol. 33, no. 1, pp. 1564-1566, 2010년 4월.
46. 이영주, 김태환, 박강우, 임고은, 박인철, “A Fully-integrated Reader System for Mobile UHF RFID,” 한국반도체학술대회 논문집, 2010년 2월.
47. 김태환, 박인철, “Area-Efficient Architecture for Joint Estimation of Fine Timing and Integer Carrier Offsets,” 한국반도체학술대회 논문집, 2007년 2월.

📋 Patents

1. 김태환, 이수정, 이소혜, 이지영, “특징맵의 지역성을 고려한 신경망 추론 고속화 장치 및 방법 (APPARATUS AND METHOD FOR ACCELERATING NEURAL NETWORK INFERENCE PROCESS BASED ON FEATURE MAP LOCALITY),” 대한민국(South Korea), Pending, 10-2024-0059617, 5/7/2024.
2. 김태환, 곽길호, “특징맵의 지역성을 고려한 신경망 추론 과정의 오류 정정 장치 및 방법 (APPARATUS AND METHOD FOR CORRECTING ERROR IN NEURAL NETWORK INFERENCE PROCESS BASED ON FEATURE MAP LOCALITY),” 대한민국(South Korea), Pending, 10-2024-0057816, 4/30/2024.
3. 김태환, 오선희, “신경망 추론 과정의 연산 생략 장치 및 방법 (APPARATUS AND METHOD FOR SKIPPING OPERATION IN NEURAL),” 대한민국(South Korea), Pending, 10-2023-0057612, 5/3/2023.
4. 김태환, 김지호, “명령어 집합 기반의 신경망 추론 프로세서에 대한 동적 프루닝 장치 및 방법 (DYNAMIC PRUNING APPARATUS AND METHOD FOR),” 대한민국(South Korea), Pending, 10-2022-0080201, 6/30/2022.
5. 김태환, 최경찬, 이수정, “효율적인 주소 변환 기능을 구비한 신경망 추론 가속 장치 및 방법 (Apparatus and method for accelerating neural network inference based on efficient address translation),” 대한민국(South Korea), Pending, 1-2022-0023476, 2/23/2022.
6. 김태환, 박상준, “이진화 컨볼루션 신경망의 공간적 인접성을 이용한 연산 속도 향상 장치 및 방법 (APPARATUS AND METHOD FOR IMPROVING COMPUTATION SPEED USING LOCALITY-EXPLOITING TECHNIQUE IN BINARIZED NEURAL NETWORK),” 대한민국(South Korea), Pending, 10-2021-0136456, 10/14/2021.
7. 김태환, 김지호, “재귀신경망의 활성화 함수 구현 장치 및 방법 (APPARATUS AND METHOD FOR HADWARE IMPLEMENTATION OF ACTIVATION FUNCTION IN RECURRENT NEURAL NETWORK),” 대한민국(South Korea), Pending, 10-2021-0055683, 4/29/2020.
8. 김태환, 류창호, “클리핑을 고려한 이진화 신경망 학습 장치 및 방법 (APPARATUS AND METHOD FOR TRAINING BINARY NEURAL NETWORK BASED ON CLIPPING-AWARE WEIGHT UPDATE),” 대한민국(South Korea), Pending, 10-2020-0133474, 10/15/2020.
9. 김태환, 김지호, “신경망 모델의 추론속도 향상 장치 및 방법 (APPARATUS AND METHOD FOR IMPROVING INFERENCE SPEED OF NEURAL NETWORK MODEL),” 대한민국(South Korea), Pending, 10-2020-0052268, 4/29/2020.
10. 김태환, 김진원, “연속제거 극복호기의 스토리지 구조를 갖는 장치 및 연속 제거 극 복호기의 스토리지 구조를 이용한 데이터 처리 방법 (Apparatus Having Stroage Architecture for Successive-Cancellation Polar Decoder and Data Processing Method Using Storage Architecture for Successive-Cancellation Polar Decoder),” 대한민국(South Korea), Registered, 10-2242762, 12/17/2019.
11. 김태환, 신지훈, “이진화된 컨벌루션 신경망의 추론속도 향상 장치 및 방법 (Device and Method for Enhancing Deduction Speed of Binarized Convolutional Neural Network),” 대한민국(South Korea), Registered, 10-2019-002409, 2/28/2019.
12. 김태환, 신지훈, “기계 상태 모니터링 장치 및 방법 (Device and Method for Mechanical Status Monitoring),” 대한민국(South Korea), Registered, 10-2018-0057194, 5/18/2018.
13. 김태환, 신지훈, “컨벌루션 신경망의 첫번째 레이어의 개선된 이진화 장치 및 방법 (Improved Binarization Apparatus and Method of First Layer of Convolution Neural Network),” 대한민국(South Korea), Registered, 10-2018-0041588, 4/10/2018.
14. 김태환, 황승준, “저전력 연속제거 극부호기를 위한 포화인식 LLR 처리 장치 및 방법 (Saturation-Aware LLR Processing Apparatus and Method for Low-Power Successive Cancellation Polar Decoder), 대한민국(South Korea), Registered, 10-2018-0040510, 4/6/2018.
15. 김태환, 윤혜연, 황승준, “연속제거 극 복호기를 위한 LLR 여분표현기법, 이를 이용한 극 부호 복호 방법 및 극 복호화기 (Polar Decoding Method and Device Using Redundant LLR Representation for Efficient Succssive-Cancellation Polar Decoder), 대한민국(South Korea), Registered, 10-2017-0172054, 12/14/2017.
16. 김태환, 박용민, 김성찬, 신지훈, “컨벌루션 신경망 기반의 이진화 연산장치 및 방법 (Device and Method for Binarization Computation of Convolutional Neural Network,” 대한민국(South Korea), Registered, 10-2017-0170505, 12/12/2017.
17. 김태환, 윤혜연, “다중 안테나 시스템에서의 극 부호를 이용한 심볼검파 및 채널 디코딩의 복합 처리 방법 및 그를 이용한 수신기 (Joint Detection and Decoding Method with Polar Codes in Multiple Input Multiple Output System and Receiver Using Thereof), 대한민국(South Korea), Pending, 10-2017-0098932, 8/4/2017.
18. 김태환, 김민상, 박용민, “안개 제거를 위한 대기 강도 추정 장치 및 방법 (Airlight estimation apparatus and method for dehazing),” 대한민국 (South Korea), Registered, 10-2016-0166418, 12/8/2016.
19. 김태환, 김원태, 박용민, 김민상, 김병오, “개선된 메디안 다크 채널 프라이어에 기반한 안개 제거 방법 및 장치 (Dehazing Method and Device Based on Improved Median Dark Channel Prior),” 대한민국 (South Korea), Registered, 10-2016-0068703, 6/2/2016.
20. 김태환, 김원태, 박용민, 김민상, 김병오, “선택적 대기 강도 추정에 기반한 안개 제거 방법 및 장치 (Dehazing Method and Device Based on Selective Atmospheric Light Estimation),” 대한민국 (South Korea), Registered, 10-2016-0068667, 6/2/2016.
21. 김태환, 이광호, 윤혜연, 김한슬, “일반화된 공간 변조 다중 안테나 시스템에서의 심볼 검파 방법 및 그를 이용한 수신기 (Symbol Detection Method in Generalized Spatial Modulation Multiple Input Multiple Output System and Reeiver Using Thereof),” 대한민국 (South Korea), Registered, 10-2016-0055325, 5/4/2016.
22. 문선아, 김원태, 김태환, “이중 다크 채널에 기반한 안개 제거 방법 및 장치 (Haze Removal Method and Device based on Dual Dark Channel),” 대한민국 (South Korea), Registered, 1020150121515, 8/28/2015, 10-1689562, 12/20/2016.
23. 김태환, 김범석, 이광호, “공간 변조 다중 입출력 시스템에서의 신호 검출 방법 (Method for Detecting Signal in Spatial Modulation Multiple-Input Mutiple-Output Systems),” 대한민국 (South Korea)Registered, 1020150045655, 3/31/2015, 101632882, 6/17/2016.
24. 김태환, 이광호, “공간 변조 시스템의 활성 안테나 검파 방법 (Activated Antenna Detection Method in Spatial Modulation Systems),” 대한민국 (South Korea), Registered, 1020140159759, 11/17/2014, 1015738270000, 11/26/2015.
25. 김태환, 이광호, 정광현, “공간 변조 시스템의 심볼 검파 방법 (Symbol Detection Method in Spatial Modulation Systems),” 대한민국 (South Korea), Registered, 1020140134416, 10/6/2014, 1015850750000, 1/7/2016.
26. 김태환, 김진휘, “다중 입력 다중 출력 통신시스템의 동적 시간 스케줄링방법 (Method for Runtime Scheduling of Multiple-Input Multiple-Output Systems),” 대한민국 (South Korea), Registered, 1020140047795, 4/22/2014, 10-1609691, 3/31/2016.
27. 김태환, 김원태, 이광호, “렌즈 왜곡 보정을 위한 메모리 인터페이스 장치 및 방법 (Device and Method of a Memory Interface for Lens Distortion Correction),” 대한민국 (South Korea), Registered, 1020130108529, 9/10/2013, 1015200410000, 5/7/2015.
28. 김태환, 정희성, “디모자이크가 결합된 렌즈 왜곡 보정 장치 및 방법, (Device and Method for the Joint Color Demosaic and Lens Distortion Correction),” 대한민국 (South Korea), Registered, 1020130108971, 9/11/2013, 1015687430000, 11/6/2015.
29. 김태환, 조원희, “다중 입력 다중 출력 시스템을 위한 낮은 복잡도의 비용함수 계산방법 (Low-Complexity Cost Function Calculation Method for Multiple-Input Multiple-Output Systems),” 대한민국 (South Korea), Registered, 1020130083539, 7/16/2013, 1014835680000, 1/12/2015.
30. 김태환, 김원태, 배현우, “전달량 보정에 기반한 고품질 안개 제거장치 및 그 방법 (High-Quality Haze Removal Based on Transmission Correction High-quality haze removal apparatus based on transmission correction and method thereof),” 대한민국 (South Korea), Pending, 1020140082257, 7/2/2014.
31. 김태환, “렌즈 왜곡 보정 장치 및 밥법 (Apparatus and Method for Correcting Lens Distortion),” 대한민국 (South Korea), Registered, 1020120145805, 8/4/2014, 1014285340000, 6/23/2014.
32. 김태환, “다중 입력 다중 출력 통신 시스템의 심볼 검파 방법 (Symbol Detection Method for MIMO Systems),” 대한민국 (South Korea), Registered, 1020120066965, 6/21/2012, 1013515770000, 1/8/2014.
33. 김태환, “다중 입력 다중 출력 통신 시스템의 심볼 검파 방법 (Symbol Detection Method for MIMO Systems),” 대한민국 (South Korea), Registered, 1020120065487, 6/19/2012, 1013713150000, 3/3/2014.
34. 김태환, “다중 입력 다중 출력 시스템의 연판정 심볼 검파 방법 (Soft-Output Symbol Detection Method for MIMO Systems),” 대한민국 (South Korea), Registered, 1020120043491, 4/25/2012, 1013724090000, 11/4/2013.
35. 박인철, 김태환, “렌즈 식별번호를 이용한 렌즈 왜곡 보정 장치, 이를 포함하는 카메라 및 렌즈 왜곡 보정 방법, (Lens Distortion Correction Device Using Lens Identification Number, Camera Employing the Same and Method for Correcting Lens Distortion),” 대한민국 (South Korea), Registered, 1020100032083, 4/8/2010, 1010900970000, 11/30/2011.
36. 박인철, 김은찬, 김봉진, 김태환, “일관성 관리 방법, 일관성 관리 회로, 이를 포함하는 캐시 장치 및 반도체 장치 (Method for managing coherence, coherence management unit, cache device and semiconductor device including the same),” 대한민국 (South Korea), Registered, 1020100011423, 2/8/2010, 1010929290000, 12/6/2011.
37. 박인철, 김태환, 이영주, “딜레이 액세스 지원 장치, 딜레이 액세스 지원 방법 및 딜레이 엑세스를 지원하는 소리 합성 장치 (Apparatus of Supporting Delay Access, Method of Supporting Delay Access and Sound Synthesis Apparatus of Supporting Delay Access),” 대한민국 (South Korea), Registered, 1020080057404, 6/18/2008, 1009410810000, 2/1/2010.
38. 박인철, 김태환, 이영주, “프로그래머블 소리 합성 장치 및 프로그래머블 소리 합성 방법 (Programmable Sound Synthesis Apparatus and Programmable Sound Synthesis Method),” 대한민국 (South Korea), Registered, 1020080049065, 5/27/2008, 1009680900000, 6/29/2010.
39. 박인철, 김태환, 김은찬, 김봉진, “싱글 코어용 캐시 컨트롤러를 이용한 멀티 코어용 캐시 회로, 이를 포함하는 캐시 장치, 반도체 장치 및 캐시 메모리 제어 방법 (Multi-core Cache Circuit Using Single-core Cache Controller, Cache Device and Semiconductor Device Including the Same, and method for Controlling the Cache Memory),” 대한민국 (South Korea), Registered, 1020100006038, 1/22/2010, 1010431990000, 6/15/2011.
40. 박인철, 김봉진, 김태환, 김은찬, “메모리 관리 유닛 제어 장치, 이를 포함하는 멀티 코어 프로세서, 컴퓨터 시스템 및 메모리 관리 유닛 제어 방법, (Apparatus for Controlling Memory Management Unit, Multi-core Processor and Computer System Including the Same, and Method of Controlling Memory Management Unit),” 대한민국 (South Korea), Registered, 1020100006031, 1/22/2010, 1011038180000, 1/2/2012.
41. 박인철, 김태환, “논리회로 파일 자동 변환 방법 및 장치 (Method and apparatus of converting a spreadsheet file into a hardware description language file),” 대한민국 (South Korea), Registered, 1020070047374, 5/16/2007, 1009072240000, 7/3/2009.

👔 Professional Activities

• Member of Review Board for National Research Foundation (NRF) of Korea
  • Oct. 2024 - Present.
• Associate Editor for IEIE Trans. Smart Processing & Computing
  • Jan. 2020 - Present
• Associate Editor for Journal of the Institute of Electronics and Information Engineers
  • Jan. 2023 - Present
• Operational Manager in Advanced Broadcasting Media Technology Research Center, Gyeonggi-do Regional Research Center (GRRC)
  • July 2013 - June 2016.
• Program Director in Info. Engineering Program for Accreditation Board for Engineering Education of Korea, Korea Aerospace University
  • Mar. 2015 - Feb. 2016.
• IEEE Member
  • Aug. 2010 - Present.
• IEICE Member
  • Aug. 2010 - Present.
• IEIE Life Member
  • Aug. 2010 - Present.
• ISE Life Member
  • July, 2017 - Present.

💾 Recent Projects (2017 – Present)

• Study of FPGA-Based Fault-Tolerant Binary NPU for Space AI Applications
  • Aug. 2025 - July 2028, National Research Foundation, Korea
  • Principal Investigator
  • This study aims to develop an FPGA-based fault-tolerant binary neural network processing unit (NPU) for space AI applications and to achieve high reliability even on low-cost commercial-grade FPGAs through a new architecture based on neural network redundancy and activation estimation.
• Study of Micro NPU for Tiny MCU
  • July 2021 - June 2022, ABOV Semiconductor, Korea
  • Principal Investigator
  • This project aims to design and implement a micro NPU IP, envisioning tiny MCU integration. The NPU supports the resource and energy-efficient inference process based on binary neural networks of various types. The target complexity is below 15K GE and the target speed is higher than 200 GOP/s, while the inference accuracy is not lower than 88% for the CIFAR10 classification task.
• Study of Inference and Training Processors for Binary Neural Networks in a Resource-Limited FPGA
  • June 2016 - Feb. 2024, National Research Foundation, Korea
  • Principal Investigator
  • This project aims to implement and validate a highly resource-efficient binary neural network inference/learning acceleration processor for low-cost FPGAs with extremely limited available resources. The performance targets are: 1) implementation and validation of a binary neural network inference acceleration processor with a resource efficiency of >50 MOP/s/LUT; 2) implementation and validation of a binary neural network learning acceleration processor with a resource efficiency of >2 MFLOP/s/LUT and energy efficiency of >150 GFLOP/J; and 3) implementation and validation of an acceleration processor capable of processing inference/learning of binary neural networks. The processor aims to achieve the same inference/learning speedup as existing individual processors, but at 80% or less of the sum of existing results in terms of resource usage.
• Study of High-Performance Channel Decoding Processor for Next-Generation Communication and Storage Systems
  • Nov. 2018 - Oct. 2021, National Research Foundation, Korea
  • Principal Investigator
  • Polar coding has been adopted for 5G communications systems and is likely to be applied to high-performance storage systems. This research aims to advance the polar code decoding technology, which is one of the outputs developed in the previous project, and improve and optimize it to meet the high-speed, low-complexity, low-power performance requirements of 5G communication systems and high-performance storage systems. Identify the performance requirements of polar code decoding technology in the controllers of 5G communication systems and next-generation SSD systems based on NAND flash memory, and improve the architecture to improve the error rate performance and reduce the hardware complexity of previously developed polar code decoding algorithms. Design a decoding processor for the application system, verify its functionality and evaluate its performance. Fabricated a prototype ASIC / FPGA based on the developed decoding processor to demonstrate its functionality and performance at the actual chip level to gain credibility for the dissemination of the results.
• Study of Joint Detection and Decoding for Next-Generation MIMO Communication Systems
  • Nov. 2015 - Oct. 2018, National Research Foundation, Korea
  • Principal Investigator
  • This study will develop a new efficient scheme to perform joint symbol detection and channel decoding for next-generation wireless communication systems. In addition, a processor shall be designed and implemented based on the new scheme, which will prove the validity the scheme. In the previous studies, the detection and the decoding have been treated separately even though they are performed in a similar fashion. In this study, a new scheme will be developed in order to combine the detection and the detection, so that the overall computational complexity may be reduced while improving the error-rate performance. Furthermore, a dedicated processor shall be developed based on the new scheme. As the processor shall be designed and implemented targeting the next-generation WLAN systems (IEEE 802.11ah), the achievements of this study can be imported usefully in order to develop other large-scale modem SoC.

The information of the other projects before 2017 could be provided on request.

🎯 References

Provided on request.